The present invention generally relates to a serial data receiver used in the transmission/reception of serial data.
FIG. 1 is a block diagram showing an arrangement of a conventional serial data receiver. The serial data receiver is mounted in a master device 401. A serial port ROM 402 as a slave device is connected to a data terminal 403 and a clock terminal 404, both of which are provided in the master device 401, via a data wiring line 405 and a clock wiring line 406. A frequency divider 407 provided in the master device 401 generates a clock and supplies the generated clock to respective circuits including a shift register 408 in the master device 401. The frequency divider 407 also supplies the generated clock from the clock terminal 404 to the serial port ROM 402 via the clock wiring line 406. The shift register 408 provided in the master device 401 receives a serial data from the serial port ROM 402 via the data wiring line 405 and data terminal 403. The received serial data is stored in a data register 409. Thereby, the serial data receiving operation is completed. When the received serial data is used in the master device 401, a read signal 410 inputted to a three-state buffer 411 via a data read enable terminal 419 is made to be active. Thereby, the received serial data is outputted from the data register 409 onto a data bus 412 via the three-state buffer 411. The received serial data outputted on the data bus 412 is outputted to the outside via a data bus output terminal 420. A control circuit 413 controls the respective circuits in the master device 401, and controls the serial port ROM 402. The control circuit 413 and the serial port ROM 402 are connected via a line which connects a slave output enable terminal 414 and an output enable terminal 415 of the serial port ROM 402.
A data reception rate in the above-mentioned serial data receiving operation is externally set in the frequency divider 407 through data reception rate setting terminals 416 and 417 provided in the master device 401. A reception data length is externally set in the frequency divider 407 through a reception data length setting terminal 418. In the master device 401, since the two data reception rate setting terminals 416 and 417 are provided, a maximum of four data reception rates can be externally set. Since the single reception data length setting terminal 418 is provided, a maximum of two reception data lengths can be externally set.
In the serial data receiver, however, the setting of the data reception rate and reception data length is carried out externally via the data reception rate setting terminals 416 and 417 and reception data length setting terminal 418, so that the manual setting work is required. For this reason, when a data transmission rate and reception data length of the slave device (the serial port ROM 402) connected to the master device 401 are modified, this involves a problem that a user must again set the data reception rate and reception data length.
Further, when the master device 401 is made in the form of an LSI, several external pins must be provided. In this case, when its cost requirement is severe, this results in one of causes of increasing its costs because it is necessary to increase the chip size, the number of pins and the package size.
Furthermore, there is a case where in order to reduce the number of necessary pins, the data reception rate is fixed according to the specification of the lowest data transmission rate of one among the slave devices which are possibly connected to the serial data receiver. In this case, the performance of the slave device cannot be fully delivered to its maximum level, so that the communication time is prolonged. This undesirably leads to the fact that the process after receiving data is delayed.
In the present invention, in order to attain the above object, a data reception rate and/or a reception data length when the serial data receiver receives the second and subsequent data of serial data are determined by specifying the first one of serial data as a judgment data and providing judgment means in the conventional serial data receiver. Thereby, it is easily optimized the reception condition of the second and subsequent data of the serial data using the first data thereof as the judgment data. Accordingly, the need for providing a terminal for setting of the reception condition can be eliminated, and the function of a slave device (serial data transmitter) connected to the serial data receiver can be delivered to its maximum level.
A serial data receiver according to a first aspect of the present invention, when receiving serial data, uses a first-received data of the serial data as a judgment data, and determines a data reception rate when receiving second and subsequent data thereof according to a decoded result of the judgment data. Thereby, the serial data receiver can set the data reception rate without providing any data reception rate setting terminal.
A serial data receiver according to a second aspect of the present invention, when receiving serial data, uses a first-received data of the serial data as a judgment data, and determines a reception data length when receiving second and subsequent data thereof according to a decoded result of the judgment data. Thereby, the serial data receiver can set the reception data length without providing any reception data length setting terminal.
A serial data receiver according to a third aspect of the present invention, when receiving serial data, uses a first-received data of the serial data as a judgment data, and determines a data reception rate and a reception data length when receiving second and subsequent data thereof according to a decoded result of the judgment data. Thereby, the serial data receiver can set the receive data rate and reception data length without providing any terminals for setting of the receive data rate and reception data length.
A serial data receiver according to a fourth aspect of the present invention comprises: a shift register for receiving serial data from an outside; a decoder for judging a transmission rate of data first received by the shift register; a state register for storing a judgment result of the decoder; and a control circuit for determining at least one of a reception rate and reception data length for second and subsequent data based on a value stored in the state register. Thereby, the serial data receiver can set the reception rate and/or the reception data length without providing any terminals for setting of the reception rate and reception data length.